Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
A fault simulator for MOS LSI circuits
DAC '82 Proceedings of the 19th Design Automation Conference
On computing optimized input probabilities for random tests
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits
IEEE Transactions on Computers
On Computing Signal Probability and Detection Probability of Stuck-At Faults
IEEE Transactions on Computers
On the distribution of fault coverage and test length in random testing of combinational circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Fault Coverage and Test Length Estimation for Random Pattern Testing
IEEE Transactions on Computers - Special issue on fault-tolerant computing
On adaptive diagnostic test generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Switch level random pattern testability analysis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
SIMMOS: a multiple-delay switch-level simulator
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A workstation-mixed model circuit simulator
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Mixed-level fault coverage estimation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Optimal order of the VLSI IC testing sequence
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
The Reliability of Approximate Testability Measures
IEEE Design & Test
Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes
IEEE Transactions on Computers
Functional testing techniques for digital LSI/VLSI systems
DAC '84 Proceedings of the 21st Design Automation Conference
PROOFS: a super fast fault simulator for sequential circuits
EURO-DAC '90 Proceedings of the conference on European design automation
On probabilistic switch-level simulation for asynchronous circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Fault isolation in grey systems
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
What is the path to fast fault simulation?
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Multiple distributions for biased random test patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
WTPGA: a novel weighted test-pattern generation approach for VLSI built-in self test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
D3FS: a demand driven deductive fault simulator
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Applications of testability analysis: from ATPG to critical delay path tracing
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Testability analysis: what role should it play in IC design?
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
The importance of fault simulation
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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STAtistical Fault ANalysis (STAFAN) is proposed as an alternative to fault simulation of digital circuits. In this analysis, controllabilities and observabilities of circuit nodes are defined as probabilities which are estimated from signal statistics obtained from fault-free simulation. Special procedures are developed for dealing with these quantities at fanout nodes and at feedback nodes. The computed probabilities are used to derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors. Fault coverage and the undetected fault data obtained from STAFAN for actual circuits are shown to agree favorably with the fault simulator results. The computational complexity added to a fault-free simulator by STAFAN grows only linearly with the number of circuit nodes.