WTPGA: a novel weighted test-pattern generation approach for VLSI built-in self test

Authors:
Fardad Siavoshi
Affiliations:
Jet Propulsion Laboratory, California Institute of Technology, Pasadena, California
Venue:
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Year:
1988

Citing 4
Cited 1

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On methods to match a test pattern generator to a circuit-under-test

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Abstract

A Weighted test-pattern generation approach (WTPGA) is proposed in this paper. Our motivation in proposing WTPGA is its improvement in the length of the test vector set and in the detection of random pattern resistant faults.