Built in test for VLSI: pseudorandom techniques
Built in test for VLSI: pseudorandom techniques
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning
DAC '93 Proceedings of the 30th international Design Automation Conference
Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Structured Logic Testing
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Transformed pseudo-random patterns for BIST
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Multiple distributions for biased random test patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Fault detection effectiveness of weighted random patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
WTPGA: a novel weighted test-pattern generation approach for VLSI built-in self test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
IEEE Transactions on Computers
Design of test pattern generators for built-in test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
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Autonomous circuits such as linear feedback shift registers (LFSR's) and cellular automata are used as low-cost test pattern generators for circuits testable by pseudo-random patterns. We demonstrate that different LFSR's of the same degree, started from different initial states, may yield significantly different fault coverages and test lengths when used as test pattern generators for a given circuit, especially when the circuit has faults which are hard to detect by a practical number of pseudo-random patterns. Methods to tailor an LFSR to a circuitunder-test are proposed, that attempt to select the most effective LFSR and initial state for the circuit. The first method is based on a learning process that can be applied directly to certain types of circuits. The learning process is also used to establish a collection of (primitive and nonprimitive) LFSR's and initial states, effective for arbitrary circuits. This collection can then be used as a starting point for a genetic optimization procedure aimed at improving the selected LFSR and initial state. The use of an LFSR that can apply complemented as well as uncomplemented test patterns is shown to significantly improve the fault coverage, at the cost of a small area overhead. Experimental results demonstrate the applicability of the proposed approaches to stuck-at faults and to transition faults.