Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Test generation for path delay faults based on learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing
IEEE Transactions on Computers
On methods to match a test pattern generator to a circuit-under-test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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