Digital logic testing and simulation
Digital logic testing and simulation
Split circuit model for test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Freeze!: a new approach for testing sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Test function specification in synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Enhanced controllability for IDDQ test sets using partial scan
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Finite state machine synthesis with fault tolerant test function
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
SEESIM—a fast synchronous sequential circuit fault simulator with single event equivalence
EURO-DAC '92 Proceedings of the conference on European design automation
INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning
DAC '93 Proceedings of the 30th international Design Automation Conference
Sequential circuit test generation on a distributed system
DAC '93 Proceedings of the 30th international Design Automation Conference
A cost-based approach to partial scan
DAC '93 Proceedings of the 30th international Design Automation Conference
A fast and memory-efficient diagnostic fault simulation for sequential circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Symbolic exploration of large circuits with enhanced forward/backward traversals
EURO-DAC '94 Proceedings of the conference on European design automation
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
New methods of improving parallel fault simulation in synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algorithms to compute bridging fault coverage of IDDQ test sets
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Novel Approach to Random Pattern Testing of Sequential Circuits
IEEE Transactions on Computers
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Techniques for improving the efficiency of sequential circuit test generation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits
IEEE Transactions on Computers
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Deterministic test pattern generation techniques for sequential circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Application of Homing Sequences to Synchronous Sequential Circuit Testing
IEEE Transactions on Computers
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
Testability forecasting for sequential circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Gate delay fault test generation for non-scan circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Functional test generation for non-scan sequential circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
An asynchronous algorithm for sequential circuit test generation on a network of workstations
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Generation of search state equivalence for automatic test pattern generation
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Dynamic test Sequence compaction for Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Deriving Signal Constraints to Accelerate Sequential Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Multiple Faults: Modeling, Simulation and Test
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Exclusive Test and its Applications to Fault Diagnosis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
8.2 On Synchronizing Sequences and Test Sequence Partitioning
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Combinational Test Generation for Various Classes of Acyclic Sequential Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Fault Simulation of IDDQ Tests for Bridging Faults in Sequential Circuits
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
LOCSTEP: A Logic Simulation-Based Test Generation Procedure
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
A New Approach to Test Generation and Test Compaction for Scan Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Double-single stuck-at faults: a delay fault model for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TOV: sequential test generation by ordering of test vectors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A study of IDDQ subset selection algorithms for bridging faults
ITC'94 Proceedings of the 1994 international conference on Test
Full symbolic ATPG for large circuits
ITC'94 Proceedings of the 1994 international conference on Test
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 4.12 |
A description is given of Gentest, with emphasis on STG2, a sequential test generator that uses the Back test-generation algorithm and the Split value model. The performance of STG2 on a Convex C-1 computer is compared with that of its predecessor, STG1 and STG1.5. Results are also presented for another set of experiments for Gentest on a Sun 3/60 workstation.