On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Static compaction using overlapped restoration and segment pruning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Overall consideration of scan design and test generation
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An algorithm to reduce test application time in full scan designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Techniques for improving the efficiency of sequential circuit test generation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Simulation based test generation for scan designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Reduced Scan Shift: A New Testing Method for Sequential Circuit
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Selectable Length Partial Scan: A Method to Reduce Vector Length
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Serial-Scan Test-Vector-Compression Methodology
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Proceedings of the IEEE International Test Conference 2001
New Static Compaction Techniques of Test Sequences for Sequential Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Vector restoration based static compaction of test sequences for synchronous sequential circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test application time reduction for sequential circuits with scan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
N-detection under transparent-scan
Proceedings of the 42nd annual Design Automation Conference
Test compaction for transition faults under transparent-scan
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reducing the switching activity of test sequences under transparent-scan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors. Under this approach, the scan-in, scan-select and scan-out lines are treated as conventional primary inputs or primary outputs of the circuit. As a result, limited scan operations, where scan chains are shifted a number of times smaller than their lengths, are incorporated naturally into the test sequences generated by this approach. This leads to very aggressive compaction, resulting in test sequences with the lowest known test application times for benchmark circuits.