An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Selectable Length Partial Scan: A Method to Reduce Vector Length
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
Algorithms to compute bridging fault coverage of IDDQ test sets
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Functional test generation for full scan circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
IEEE Transactions on Computers
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
An approach to test compaction for scan circuits that enhances at-speed testing
Proceedings of the 38th annual Design Automation Conference
On identifying don't care inputs of test patterns for combinational circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On undetectable faults in partial scan circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A New Approach to Test Generation and Test Compaction for Scan Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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