On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An algorithm to reduce test application time in full scan designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Simulation based test generation for scan designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Finding Undetectable and Redundant Faults in Synchronous Sequential Circuits
ICCD '98 Proceedings of the International Conference on Computer Design
Combinational ATPG theorems for identifying untestable faults in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
We provide a definition of undetectable faults in partial scan circuits under a test application scheme where a test consists of primary input vectors applied at-speed between scan operations. We also provide sufficient conditions for a fault to be undetectable under this test application scheme. We present experimental results on finite-state machine benchmarks to demonstrate the effectiveness of these conditions in identifying undetectable faults.