The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Sequential redundancy identification using recursive learning
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization for low power using local logic transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Sequential optimisation without state space exploration
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Techniques for improving the efficiency of sequential circuit test generation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
A Methodology to Design Efficient BIST Test Pattern Generators
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Efficient Identification of Non-Robustly Untestable Path Delay Faults
Proceedings of the IEEE International Test Conference
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG
ATS '97 Proceedings of the 6th Asian Test Symposium
MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On Finding Undetectable and Redundant Faults in Synchronous Sequential Circuits
ICCD '98 Proceedings of the International Conference on Computer Design
Identifying sequentially untestable faults using illegal states
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
LOCSTEP: a logic-simulation-based test generation procedure
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On undetectable faults in partial scan circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Untestable fault identification through enhanced necessary value assignments
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
On test generation by input cube avoidance
Proceedings of the conference on Design, automation and test in Europe
Dynamic test compaction for a random test generation procedure with input cube avoidance
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Random test generation with input cube avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
Journal of Electronic Testing: Theory and Applications
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This paper we present MUST-a multiple-stem analysis algorithm for identifying untestable faults is the mosttime-consuming part of a sequential ATPG.MUST extends the scope of the single-stem analysis done inthe FIRES algorithmby identifying additional untestablefaults that cannot be found by single-stem analysis.