LSS: a system for production logic synthesis
IBM Journal of Research and Development
NEST: A non-enumerative test generation method for path delay faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
On testing delay faults in macro-based combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RESIST: a recursive test pattern generation algorithm for path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
Test generation for path delay faults based on learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Efficient Path Selection for Delay Testing Based on Path Clustering
Journal of Electronic Testing: Theory and Applications
Correlations between path delays and the accuracy of performance prediction
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A BIST approach to delay fault testing with reduced test length
EDTC '95 Proceedings of the 1995 European conference on Design and Test
An efficient method for computing exact path delay fault coverage
EDTC '95 Proceedings of the 1995 European conference on Design and Test
9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Design for Testability in Nanometer Technologies; Searching for Quality
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Longest path selection for delay test under process variation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Low Voltage Test in Place of Fast Clock in DDSI Delay Test
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Performance verification of high-performance ASICs using at-speed structural test
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
a fuzzy model for path delay fault detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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