Performance verification of high-performance ASICs using at-speed structural test

Authors:
Vikram Iyengar;Mark Johnson;Theo Anemikos;Bob Bassett;Mike Degregorio;Rudy Farmer;Gary Grise;Phil Stevens;Mark Taylor;Frank Woytowich
Affiliations:
IBM Microelectronics, Essex Junction, VT;IBM Microelectronics, Essex Junction, VT;IBM Microelectronics, Essex Junction, VT;IBM Microelectronics, Essex Junction, VT;IBM Microelectronics, Essex Junction, VT;IBM Microelectronics, Essex Junction, VT;IBM Microelectronics, Essex Junction, VT;IBM Microelectronics, Essex Junction, VT;IBM Microelectronics, Essex Junction, VT;IBM Microelectronics, Essex Junction, VT
Venue:
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Year:
2006

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Abstract

Performance verification is becoming critical to high performance ASICs manufacturing. Performance verification ensures that only those ASICs whose performance is higher than an advertized threshold are shipped to demanding customers. This provides a means to weed out nominal performance ASICs, and also ship ASICs at difference grades. However, performance verification based on functional test requires high-functionality testers that can supply multiple asynchronous clocks. Additionally, functional test requires expensive testers that can operate at the speed of the fastest clock domain on the ASIC. As an alternative, at-speed structural test can provide performance verification capability at very low cost. However, existing structural test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a scalable and flexible structural test method for performance verification of GH-speed ASICs. The proposed method requires no tight restrictions on the circuit design. Moreover, low-cost testers are used, thus sharply reducing test cost.