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Journal of Electronic Testing: Theory and Applications
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Testing of critical paths for delay faults
Proceedings of the IEEE International Test Conference 2001
Delay Testing Quality in Timing-Optimized Designs
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Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
ENHANCED DELAY DEFECT COVERAGE WITH PATH-SEGMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Comparing Functional and Structural Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Speed binning aware design methodology to improve profit under parameter variations
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Performance verification of high-performance ASICs using at-speed structural test
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Test generation in the presence of timing exceptions and constraints
Proceedings of the 44th annual Design Automation Conference
Parametric yield analysis and optimization in leakage dominated technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parametric yield management for 3D ICs: Models and strategies for improvement
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Variability driven gate sizing for binning yield optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Profit aware circuit design under process variations considering speed binning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Computer Science and Technology
Critical Path Selection for Delay Testing Considering Coupling Noise
Journal of Electronic Testing: Theory and Applications
Binning optimization based on SSTA for transparently-latched circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Correlating system test Fmax with structural test Fmax and process monitoring measurements
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Profit maximization through process variation aware high level synthesis with speed binning
Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive reduction of the frequency search space for multi-vdd digital circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Virtually-aged sampling DMR: unifying circuit failure prediction and circuit failure detection
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Journal of Electronic Testing: Theory and Applications
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Editor's note: What would it take to reduce speed binning's dependency on functional testing? One answer is a structural at-speed test approach that can achieve the same effectiveness as functional testing. The authors of this article offer a formula to relate structural critical-path testing frequency to system-operation frequency. They demonstrate that there can be a high correlation between frequencies resulting from structural testing and those resulting from functional testing.驴Li-C. Wang, University of California, Santa Barbara