Neighbor selection for variance reduction in I_DDQ and other parametric data
Proceedings of the IEEE International Test Conference 2001
Optimal production test times through adaptive test programming
Proceedings of the IEEE International Test Conference 2001
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
VARIANCE REDUCTION USING WAFER PATTERNS in IddQ DATA
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Screening MinVDD Outliers Using Feed-Forward Voltage Testing
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Speed Binning with Path Delay Test in 150-nm Technology
IEEE Design & Test
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design
ITC '04 Proceedings of the International Test Conference on International Test Conference
ITC '04 Proceedings of the International Test Conference on International Test Conference
SPEED CLUSTERING OF INTEGRATED CIRCUITS
ITC '04 Proceedings of the International Test Conference on International Test Conference
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Profit aware circuit design under process variations considering speed binning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extension of Wirtinger's Calculus to Reproducing Kernel Hilbert Spaces and the Complex Kernel LMS
IEEE Transactions on Signal Processing
A Reproducing Kernel Hilbert Space Framework for Information-Theoretic Learning
IEEE Transactions on Signal Processing
Hi-index | 0.00 |
Increasing process variations, coupled with the need for highly adaptable circuits, bring about tough new challenges in terms of circuit testing. Circuit adaptation for process and workload variability require costly characterization/test cycles for each chip, in order to extract particular Vdd/fmax behavior of the die under test. This paper aims at adaptively reducing the search space for fmax at multiple levels by reusing the information previously obtained from the DUT during test-time. The proposed adaptive solution reduces the test/characterization time and costs at no area or test overhead.