On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design

Authors:
J. Zeng;M. Abadir;A. Kolhatkar;G. Vandling;L. Wang;J. Abraham
Affiliations:
Freescale Semiconductor Inc., Austin, TX;Freescale Semiconductor Inc., Austin, TX;Freescale Semiconductor Inc., Austin, TX;Cadence Design Systems, Endicott, NY;University of California, Santa Barbara, CA;University of Texas at Austin, Austin, TX
Venue:
ITC '04 Proceedings of the International Test Conference on International Test Conference
Year:
2004

Citing 0
Cited 9

Performance verification of high-performance ASICs using at-speed structural test

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Correlating system test Fmax with structural test Fmax and process monitoring measurements

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design for testability features of godson-3 multicore microprocessor

Journal of Computer Science and Technology
A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

Journal of Electronic Testing: Theory and Applications
TSUNAMI: a light-weight on-chip structure for measuring timing uncertainty induced by noise during functional and test operations

Proceedings of the great lakes symposium on VLSI
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults

Journal of Electronic Testing: Theory and Applications
Adaptive reduction of the frequency search space for multi-vdd digital circuits

Proceedings of the Conference on Design, Automation and Test in Europe
Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield Improvement of MEMS Convective Accelerometers

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

The use of functional vectors has been an industry standard for speed binning purposes of high performance ICs. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target performance related faults in a more systematic manner. To make structural testing an effective alternative to functional testing for speed binning, structural patterns need to correlate with functional test frequencies closely. In this paper, we investigate the correlation between functional test frequency and that of various types of structural patterns onMPC7455, aMotorola processor executing to the PowerPC 1 instruction set architecture.