On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design
ITC '04 Proceedings of the International Test Conference on International Test Conference
Modeling Power Supply Noise in Delay Testing
IEEE Design & Test
Power Supply Noise in SoCs: Metrics, Management, and Measurement
IEEE Design & Test
A Production IR-Drop Screen on a Chip
IEEE Design & Test
Path-RO: a novel on-chip critical path delay measurement under process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Understanding Power Supply Droop during At-Speed Scan Testing
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Power Supply Noise: A Survey on Effects and Research
IEEE Design & Test
Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
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Noise such as voltage drop and temperature in integrated circuits can cause significant performance variation and even functional failure in lower technology nodes. In this paper, we propose a light-weight on-chip sensor that measures timing uncertainty induced by noise during functional and test operations. The proposed on-chip structure facilitates speed characterization under various workloads and test conditions. Simulation results show that it offers very high sensitivity to noise even under variations. The structure requires negligible area in the chip.