High-speed digital design: a handbook of black magic
High-speed digital design: a handbook of black magic
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Mixed Signal DFT: A Concise Overview
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
Locality-Driven Parallel Static Analysis for Power Delivery Networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay sensing for long-term variations and defects monitoring in safety---critical applications
Analog Integrated Circuits and Signal Processing
Modeling and estimation of power supply noise using linear programming
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the great lakes symposium on VLSI
Minimizing power supply noise through harmonic mappings in networks-on-chip
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A silicon-validated methodology for power delivery modeling and simulation
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.02 |
Power integrity is emerging as a major challenge in SoC designs in deep-submicron (DSM) technologies. Existing design and analysis techniques and metrics fail to provide an accurate impact estimation of power supply noise, making it difficult to optimize design and test procedures. The lack of predictability is complicating timing closure, physical design, production test, and speed-grading of SoCs. Furthermore, traditional power supply noise reduction techniques are not capable of addressing some of the new issues that have arisen in DSM. This article describes and validates two metrics that quantify the impact of power supply noise. The authors propose modified decoupling-capacitor (decap) designs and present results of silicon experimentation. They also discuss the true impact of power supply noise on production test, and present DFT techniques to reduce power supply noise during testing.