On-chip decoupling capacitor optimization using architectural level prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Noise driven in-package decoupling capacitor optimization for power integrity
Proceedings of the 2006 international symposium on Physical design
Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A high density, carbon nanotube capacitor for decoupling applications
Proceedings of the 43rd annual Design Automation Conference
Decoupling capacitor planning and sizing for noise and leakage reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Power Supply Noise in SoCs: Metrics, Management, and Measurement
IEEE Design & Test
Statistical power supply dynamic noise prediction in hierarchical power grid and package networks
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sleep transistor sizing and adaptive control for supply noise minimization considering resonance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Layout of decoupling capacitors in IP blocks for 90-nm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and design of on-chip decoupling capacitors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
The on-chip decoupling capacitors are widely used in today's high-performance microprocessor design to mitigate the power supply noise problem. The continued reduction of oxide thickness in advanced nanotechnology, however, also significantly increases the tunneling current and leakage power of thin-oxide capacitors. This paper describes the modeling and simulation of a complete chip and package power supply distribution network, and the optimization of the placement of thin-oxide and thick-oxide capacitors to reduce the tunneling current, leakage power, and burn-in cost, while limiting the power supply noise within noise margin.