Analysis and design of on-chip decoupling capacitors

Authors:
Tasreen Charania;Ajoy Opal;Manoj Sachdev
Affiliations:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada;Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada;Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2013

Citing 8
Cited 0

Power considerations in the design of the Alpha 21264 microprocessor

DAC '98 Proceedings of the 35th annual Design Automation Conference
On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction

SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Gate leakage reduction for scaled devices using transistor stacking

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Vectorless Analysis of Supply Noise Induced Delay Variation

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ESD Protection Device and Circuit Design for Advanced CMOS Technologies

ESD Protection Device and Circuit Design for Advanced CMOS Technologies
Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Layout of decoupling capacitors in IP blocks for 90-nm CMOS

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and implementation of active decoupling capacitor circuits for power supply regulation in digital ICs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Power supply noise management continues to be a challenge with the scaling of CMOS technologies. Use of on-chip decoupling capacitors (decaps) is the most common noise suppression technique and has significant associated area and leakage costs. There are numerous methods of implementing decaps and it is not always clear which implementation is the most optimal for the given design constraints. This paper characterizes various decap implementations including MOS-based decaps, multilayer metal decaps, and metal-insulator-metal decaps using postlayout simulations in a 65-nm CMOS technology, and provides an outline for determining the most optimal selection and design of decaps based on area, leakage, and location. Hybrid structures are further shown to boost the area efficiency of conventional nMOS decaps by an additional ∼25%.