High-speed digital design: a handbook of black magic
High-speed digital design: a handbook of black magic
Circuit-level techniques to control gate leakage for sub-100nm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Maximum effective distance of on-chip decoupling capacitors in power distribution grids
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
Decoupling capacitors for multi-voltage power distribution systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and Design of Digital Integrated Circuits
Analysis and Design of Digital Integrated Circuits
Optimal decoupling capacitor sizing and placement for standard-cell layout designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis and design of on-chip decoupling capacitors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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On-chip decoupling capacitors (decaps) in the form of MOS transistors are widely used to reduce power supply noise. This paper provides guidelines for standard cell layouts of decaps for use within Intellectual Property (IP) blocks in application-specific integrated circuit (ASIC) designs. At 90-nm CMOS technology and below, a tradeoff exists between high-frequency effects and electrostatic discharge (ESD) reliability when designing the layout of such decaps. In this paper, the high-frequency effects are modeled using simple equations. A metric is developed to determine the optimal number of fingers based on the frequency response. Then, a cross-coupled design is described that has been recently introduced by cell library developers to handle ESD problems. Unfortunately, it suffers from poor response times due the large resistance inherent in its design. Improved cross-coupled designs are presented that properly balance issues of frequency response with ESD performance, while greatly reducing thin-oxide gate leakage.