Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Partitioning-based approach to fast on-chip decap budgeting and minimization
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Power distribution techniques for dual VDD circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Wake-up protocols for controlling current surges in MTCMOS-based technology
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Noise driven in-package decoupling capacitor optimization for power integrity
Proceedings of the 2006 international symposium on Physical design
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Timing-aware power noise reduction in layout
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Fast decap allocation based on algebraic multigrid
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Partitioning-based decoupling capacitor budgeting via sequence of linear programming
Integration, the VLSI Journal
Decreased effectiveness of on-chip decoupling capacitance in high-frequency operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient decoupling capacitance budgeting considering operation and process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Effective radii of on-chip decoupling capacitors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decoupling capacitance allocation for timing with statistical noise model and timing analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Transition-aware decoupling-capacitor allocation in power noise reduction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Generating realistic stimuli for accurate power grid analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Passive and active reduction techniques for on-chip high-frequency digital power supply noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel hierarchical cross entropy optimization for on-chip decap budgeting
Proceedings of the 47th Design Automation Conference
An efficient decoupling capacitance optimization using piecewise polynomial models
Proceedings of the Conference on Design, Automation and Test in Europe
On-chip power network optimization with decoupling capacitors and controlled-ESRs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Analysis and reduction of supply noise fluctuations induced by embedded via-programming ROM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Runtime resonance noise reduction with current prediction enabled frequency actuator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Layout of decoupling capacitors in IP blocks for 90-nm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decoupling for power gating: sources of power noise and design strategies
Proceedings of the 48th Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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With technology scaling, the trend for high-performance integrated circuits is toward ever higher operating frequency, lower power supply voltages, and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the 2001 International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. In this paper, we propose and demonstrate an algorithm for the automated placement and sizing of decaps in application specific integrated circuit (ASIC)-like circuits. The problem is formulated as one of nonlinear optimization and is solved using a sensitivity-based quadratic programming (QP) solver. The adjoint sensitivity method is applied to calculate the first-order sensitivities. We propose a fast convolution technique based on piecewise linear (PWL) compressions of the original and adjoint waveforms. Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change in the total chip area.