Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A low-power design method using multiple supply voltages
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Layout techniques supporting the use of dual supply voltages for cell-based designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Gate-level design exploiting dual supply voltages for power-driven applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2004 international symposium on Low power electronics and design
A new algorithm for improved VDD assignment in low power dual VDD systems
Proceedings of the 2004 international symposium on Low power electronics and design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal decoupling capacitor sizing and placement for standard-cell layout designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion-aware topology optimization of structured power/ground networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplanning considering IR drop in multiple supply voltages island designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The approximation scheme for peak power driven voltage partitioning
Proceedings of the International Conference on Computer-Aided Design
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Extensive research has proposed the use of multiple on-die power supplies (VDD) for reducing power consumption in CMOS circuits. We present a detailed study and design techniques for power delivery systems in dual VDD CMOS circuits. We first show that the total current to be delivered by the voltage supplies is significantly reduced (by 27%-46%) in dual VDD circuits. This current reduction prompts various design strategies that can be employed to design the power delivery system. We describe issues that arise at the system, board and package levels and propose a high-level model for the same. We then provide a new placement driven approach for designing on-die dual VDD power grids. Compared to already existing methods, the dual VDD grids generated by our approach reduce the worst case and average voltage drop by up to 12.3% and 6.8% respectively with no area overhead and sometimes improving wire congestion. We also show that dual VDD circuits can afford lower on-die decoupling capacitance budgets.