A low-power design method using multiple supply voltages

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

DAC '98 Proceedings of the 35th annual Design Automation Conference

High performance DSPs - what's hot and what's not?

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

Synthesis of low power CMOS VLSI circuits using dual supply voltages

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Clock distribution using multiple voltages

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Low-power design methodology and applications utilizing dual supply voltages

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Low-power technology mapping for mixed-swing logic

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

On gate level power optimization using dual-supply voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low-swing clock domino logic incorporating dual supply and dual threshold voltages

Proceedings of the 39th annual Design Automation Conference

Minimum-power retiming for dual-supply CMOS circuits

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

Low-power clock distribution using multiple voltages and reduced swings

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Elements of low power design for integrated systems

Proceedings of the 2003 international symposium on Low power electronics and design

Power-aware clock tree planning

Proceedings of the 2004 international symposium on Physical design

An approach for reducing dynamic power consumption in synchronous sequential digital designs

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Low-power dual Vth pseudo dual Vdd domino circuits

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Dynamic Task-Level Voltage Scheduling Optimizations

IEEE Transactions on Computers

On-chip power distribution grids with multiple supply voltages for high performance integrated circuits

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Power-aware placement

Proceedings of the 42nd annual Design Automation Conference

Power distribution techniques for dual VDD circuits

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Low-power domino circuits using NMOS pull-up on off-critical paths

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Gate level multiple supply voltage assignment algorithm for power optimization under timing constraint

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

On-chip power distribution grids with multiple supply voltages for high-performance integrated circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A New Power-Aware Scheduling Algorithm for Distributed System

GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing

Inexact computing for ultra low-power nanometer digital circuit design

NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures

Inexact computing using probabilistic circuits: Ultra low-power digital processing

ACM Journal on Emerging Technologies in Computing Systems (JETC)