Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A low-power design method using multiple supply voltages
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Low-swing clock domino logic incorporating dual supply and dual threshold voltages
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Domino logic is a commonly used alternative to CMOS logic for designing circuits with high speed and/or low area requirements. Although it provides higher speed and lower area, domino logic has relatively higher dynamic power consumption than CMOS logic due to precharge/evaluate based operation. We propose a novel low-power domino gate design and also a methodology to use these low-power but slower gates with regular domino logic gates in combinational circuits to achieve low-power operation without changing the circuit delay. We apply our method on ISCAS'85 benchmark circuits and find that replacing the off-critical path normal domino gates with the proposed low-power gates reduces power consumption of the circuits by 20.6% on the average without affecting the circuit timing.