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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper proposes an optimum methodology forassigning supply and threshold voltages to modules in a CMOScircuit such that the overall energy consumption is minimizedfor a given delay constraint. The modules of the circuit shouldhave large enough gate depths such that the delay and energypenalties of the level shifters connecting them are negligible.Both static and dynamic energy are considered in theoptimization. Energy savings of up to 48% have been achievedon various example circuits. The first step in the optimizationfinds optimum supply and threshold voltages for each modulein the circuit. If the circuit has a large number of modules, thisstep might yield a correspondingly large number of differentsupply and threshold voltages for minimum energyconsumption. Since having a large number of different supplyand threshold voltages on an IC is not feasible in currenttechnologies, an additional step clusters the multiple voltagesobtained from the first step into a fixed number of supply andthreshold voltages (for example, 2 different supply voltagesand 2 different threshold voltages). In addition to theapplication of this method to circuit optimization, it can also beapplied to a wide range of problems with delay constraints,such as software tasks running on a dynamically variable V{DD}and V{th} processor.