On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Sizing CMOS Circuits for Increased Transient Error Tolerance
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Soft delay error analysis in logic circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Soft error reduction in combinational logic using gate resizing and flipflop selection
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A method to cope with soft errors
ICC'07 Proceedings of the 11th Conference on Proceedings of the 11th WSEAS International Conference on Circuits - Volume 11
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power
Proceedings of the 13th international symposium on Low power electronics and design
Intelligent robustness insertion for optimal transient error tolerance improvement in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Checksum-based probabilistic transient-error compensation for linear digital systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate linear model for SET critical charge estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of single-event effects in embedded processors for non-uniform fault tolerant design
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Formal modeling and reasoning for reliability analysis
Proceedings of the 47th Design Automation Conference
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and optimization of nanometer CMOS circuits for soft-error tolerance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CARROT: a tool for fast and accurate soft error rate estimation
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper presents a tool for accurate soft-error tolerance analysis of nanometer circuits (ASERTA) that can be used to estimate the soft-error tolerance of nanometer circuits consisting of millions of gates. The tolerance estimates generated by the tool match SPICE generated estimates closely while taking orders of magnitude less computation time. The second part of the paper presents a tool for soft-error tolerance optimization of nanometer circuits (SERTOPT) using the tolerance estimates generated by ASERTA. The tool finds optimal sizes, channel lengths, supply voltages and threshold voltages to be assigned to gates in a combinational circuit such that the soft-error tolerance is increased while meeting the timing constraint. Experiments on ISCAS'85 benchmark circuits showed that soft-error rate of the optimized circuit decreased by as much as 47% with marginal increase in circuit delay.