Critical charge calculations for a bipolar SRAM array
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Challenges in power-ground integrity
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Comprehensive frequency-dependent substrate noise analysis using boundary element methods
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Noise-Aware Driver Modeling for Nanometer Technology
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Proceedings of the 42nd annual Design Automation Conference
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Soft delay error analysis in logic circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Soft error reduction in combinational logic using gate resizing and flipflop selection
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA
Proceedings of the conference on Design, automation and test in Europe
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Noise separation in analog integrated circuits using independent component analysis technique
Integrated Computer-Aided Engineering
Compound noise separation in digital circuits using blind source separation
Microelectronics Journal
A fast, analytical estimator for the SEU-induced pulse width in combinational designs
Proceedings of the 45th annual Design Automation Conference
Efficient analytical determination of the SEU-induced pulse shape
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal modeling and reasoning for reliability analysis
Proceedings of the 47th Design Automation Conference
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and optimization of nanometer CMOS circuits for soft-error tolerance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Placement for immunity of transient faults in cell-based design of nanometer circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CARROT: a tool for fast and accurate soft error rate estimation
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
| Hi-index | 0.00 |
Circuits using nano-meter technologies are becoming increasingly vulnerable to signal interference from multiple noise sources as well as radiation-induced soft errors. One way to ensure reliable functioning of chips is to be able to analyze and identify the spots in the circuit which are susceptible to such effects (called "soft spots" in this paper), and to make sure such soft spots are "hardened" so as to resist multiple noise effects and soft errors. In this paper, we present a scalable soft spot analysis methodology to study the vulnerability of digital ICs exposed to nano-meter noise and transient soft errors. First, we define "softness" as an important characteristic to gauge system vulnerability. Then several key factors affecting softness are examined. Finally an efficient Automatic Soft Spot Analyzer (ASSA) is developed to obtain the softness distribution which reflects the unbalanced noise-tolerant capability of different regions in a design. The proposed methodology provides guidelines to reduction of severe nano-meter noise effects caused by aggressive design in the pre-manufacturing phase, and guidelines to selective insertion of on-line protection schemes to achieve higher robustness. The quality of the proposed soft-spot analysis technique is validated by HSPICE simulation, and its scalability is demonstrated on a commercial embedded processor.