Critical charge calculations for a bipolar SRAM array
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Latch Design for Transient Pulse Tolerance
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Flip-Flop Hardening for Space Applications
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Proceedings of the 41st annual Design Automation Conference
Logic soft errors in sub-65nm technologies design and CAD challenges
Proceedings of the 42nd annual Design Automation Conference
Soft Errors in Advanced Computer Systems
IEEE Design & Test
Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Cost-effective radiation hardening technique for combinational logic
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Logic SER Reduction through Flipflop Redesign
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
A design approach for radiation-hard digital electronics
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Soft error rate analysis for sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Latch Susceptibility to Transient Faults and New Hardening Approach
IEEE Transactions on Computers
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Journal of Electronic Testing: Theory and Applications
Soft error rate reduction using redundancy addition and removal
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
On the role of timing masking in reliable logic circuit design
Proceedings of the 45th annual Design Automation Conference
Study of the effects of MBUs on the reliability of a 150 nm SRAM device
Proceedings of the 45th annual Design Automation Conference
Hierarchical Soft Error Estimation Tool (HSEET)
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits
ETS '08 Proceedings of the 2008 13th European Test Symposium
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Soft errors in combinational logic circuits are emerging as a significant reliability problem for VLSI designs. Technology scaling trends indicate that the soft error rates (SER) of logic circuits will be dominant factor for future technology generations. SER mitigation in logic can be accomplished by optimizing either the gates inside a logic block or the flipflops present on the block boundaries. We present novel circuit optimization techniques that target these elements separately as well as in unison to reduce the SER of combinational logic circuits. First, we describe the construction of a new class of flip-flop variants that leverage the effect of temporal masking by selectively increasing the length of the latching window thereby preventing faulty transients from being registered. In contrast to previous flip-flop designs that rely on logic duplication and complicated circuit design styles, the new variants are redesigned from the library flip-flop using efficient transistor sizing. We then propose a flip-flop selection method that uses slack information at each primary output node to determine the flip-flop configuration that produces maximum SER savings. Next, we propose a gate sizing algorithm that trades off SER reduction and area overhead. This approach first computes bounds on the maximum achievable SER reduction by resizing a gate. This bound is then used to prune the circuit graph, arriving at a smaller set of candidate gates on which we perform incremental sensitivity computations to determine the gates that are the largest contributors to circuit SER. Third, we propose a unified, co-optimization approach combining flip-flop selection with the gate sizing algorithm. The joint optimization algorithm produces larger SER reductions while incurring smaller circuit overhead than either technique taken in isolation. Experimental results on a variety of benchmarks show average SER reductions of 10.7X with gate sizing, 5.7X with flip-flop assignment, and 30.1X for the combined optimization approach, with no delay penalties and area overheads within 5-6%. The runtimes for the optimization algorithms are on the order of 1-3 minutes.