Logic SER Reduction through Flipflop Redesign
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The purpose of this work is to design a Flip-flop hardened to Single Event Upset (SEU) for space radiation environment. The design hardening technique is based on the use of two Dlatch hardened both to static and dynamic SEU by the concepts of high impedance state and nMOS feedback.