Critical charge calculations for a bipolar SRAM array
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Latch Design for Transient Pulse Tolerance
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Flip-Flop Hardening for Space Applications
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Logic soft errors in sub-65nm technologies design and CAD challenges
Proceedings of the 42nd annual Design Automation Conference
Soft Errors in Advanced Computer Systems
IEEE Design & Test
Cost-effective radiation hardening technique for combinational logic
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An efficient static algorithm for computing the soft error rates of combinational circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Soft error reduction in combinational logic using gate resizing and flipflop selection
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Soft error rate reduction using redundancy addition and removal
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock skew scheduling for soft-error-tolerant sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Retiming for Soft Error Minimization Under Error-Latching Window Constraints
Proceedings of the Conference on Design, Automation and Test in Europe
A low-cost, systematic methodology for soft error robustness of logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present a new flipflop sizing scheme that efficiently immunizes combinational logic circuits from the effects of radiation induced single event transients (SET). The proposed technique leverages the effect of temporal masking by selectively increasing the length of the latching windows associated with the flipflops thereby preventing faulty transients from being registered. We propose an effective flipflop sizing scheme and construct a variety of flipflop variants that function as low-pass filters for SETs and reduce the soft error rates (SER) of combinational circuits. In contrast to previously proposed flipflop designs that rely on logic duplication and complicated circuit design styles, our method provides a simple yet highly effective mechanism for logic SER reduction while incurring very small overheads in both delay (about 5 FO4) and power (about 5%). Experimental results at the circuit level on a wide range of benchmarks show 1000X reductions in SER for small increases in circuit delay and power.