Critical charge calculations for a bipolar SRAM array

Accelerated testing for cosmic soft-error rate

IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors

Modeling the cosmic-ray-induced soft-error rate in integrated circuits: an overview

IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors

Soft-error Monte Carlo modeling program, SEMM

IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors

A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits

Proceedings of the 41st annual Design Automation Conference

Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits

IEEE Design & Test

A soft error rate analysis (SERA) methodology

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Logic SER Reduction through Flipflop Redesign

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

An efficient static algorithm for computing the soft error rates of combinational circuits

Proceedings of the conference on Design, automation and test in Europe: Proceedings

A family of cells to reduce the soft-error-rate in ternary-CAM

Proceedings of the 43rd annual Design Automation Conference

Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Soft error reduction in combinational logic using gate resizing and flipflop selection

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip

Guiding circuit level fault-tolerance design with statistical methods

Proceedings of the conference on Design, automation and test in Europe

Case study of reliability-aware and low-power design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Architecture Design for Soft Errors

Architecture Design for Soft Errors

Circuit optimization techniques to mitigate the effects of soft errors in combinational logic

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Selective replication: A lightweight technique for soft errors

ACM Transactions on Computer Systems (TOCS)

False Error Vulnerability Study of On-line Soft Error Detection Mechanisms

Journal of Electronic Testing: Theory and Applications

Soft error modeling and remediation techniques in ASIC designs

Microelectronics Journal

Design as you see FIT: system-level soft error analysis of sequential circuits

Proceedings of the Conference on Design, Automation and Test in Europe

Radiation-induced Soft Errors: A Chip-level Modeling Perspective

Foundations and Trends in Electronic Design Automation

Analysis and optimization of nanometer CMOS circuits for soft-error tolerance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low-power multiple-bit upset tolerant memory optimization

Proceedings of the International Conference on Computer-Aided Design

Single event crosstalk prediction in nanometer technologies

Analog Integrated Circuits and Signal Processing