Critical charge calculations for a bipolar SRAM array
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
An Asymmetric SRAM Cell to Lower Gate Leakage
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Soft Errors in Advanced Computer Systems
IEEE Design & Test
Analytical Semi-Empirical Model for SER Sensitivity Estimation of Deep-Submicron CMOS Circuits
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
PEDS: a parallel error detection scheme for TCAM devices
IEEE/ACM Transactions on Networking (TON)
Error detection in ternary CAMs using bloom filters
Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Network and Systems Management
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Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more problematic in future technologies. This paper presents a ternary content-addressable memory (CAM) design with high immunity to SEU. Conventionally, error-correcting codes (ECC) have been used in SRAMs to address this issue, but these techniques are not immediately applicable to CAMs because they depend on processing the full contents of the memory word outside the array, which is not possible in a normal CAM access. We propose a family of TCAM cells that reduce the SER at the cost of some area increase. An SER reduction of up to 40% can be obtained with a 18% increase of area; another design reduces the SER by 16% with only a 5% increase in area.