A family of cells to reduce the soft-error-rate in ternary-CAM
Proceedings of the 43rd annual Design Automation Conference
Improving error tolerance for multithreaded register files
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
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An analytical expression is proposed for the estimation of the soft-error rate (SER) sensitivity of circuits designed in deep-submicron CMOS technologies. The model parameters for a given technology and for a specific radiation type have been determined by combining experimental accelerated SER test results with critical charge data obtained from circuit simulations. The resulting analytical models are discussed for the cases of the alpha-induced SER of a 0.18µmprocess and for both the alpha- and neutron-induced SER of a 0.13µm process. The results indicate that the approach provides an efficient means to predict the contributions of individual nodes to the SER of a circuit. The method is shown to be effective in the evaluation of the impact of design modifications on the circuit SER.