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PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
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Proceedings of the 27th annual international symposium on Computer architecture
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The MIPS R10000 Superscalar Microprocessor
IEEE Micro
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DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
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IEEE Transactions on Dependable and Secure Computing
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HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
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HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
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IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Error-tolerance memory Microarchitecture via Dynamic Multithreading
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
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IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Thread-associative memory for multicore and multithreaded computing
Proceedings of the 2006 international symposium on Low power electronics and design
Optimal codes for single-error correction, double-adjacent-error detection
IEEE Transactions on Information Theory
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Soft-Error-Rate-Analysis (SERA) Methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR). The proposed technique exploits the interplay between the concurrent threads for runtime error control. We also present two DMR enhancements, immediate write-back and self-recovery, to address the error accumulation effect. A multithreaded register file was implemented to demonstrate the proposed DMR technique. Simulation results on the SPEC CPU2000 benchmarks demonstrate significant overhead reduction in performance and energy efficiency related to error recovery. In addition, the proposed technique features good scalability with respect to the instruction-level and thread-level parallelism for next-generation processor design, where the soft error problem is expected to get worse due to technology scaling and architecture-affecting trends.