Accurate Estimation of Soft Error Rate (SER) in VLSI Circuits

Authors:
Wayne Burleson;Israel Koren;Atul Maheshwari
Affiliations:
University of Massachusetts, Amherst;University of Massachusetts, Amherst;University of Massachusetts, Amherst
Venue:
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Year:
2004

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Cited 2

Improving error tolerance for multithreaded register files

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An infrastructure for accurate characterization of single-event transients in digital circuits

Microprocessors & Microsystems

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Abstract

Trends in CMOS technology have resulted in circuits with higher soft error rate (SER), makingit imperative to accurately estimate the SER of VLSI circuits.In this paper a comparativestudy is presented between the Q{crit} method and the simulation method for estimating the circuit level SER.It is shown that for small circuits with uniformly distributed output values(e.g. Flip-flop, binary counter), both methods provide similar estimates for SER.However, for other circuits the Q{crit}-based method provides SER estimates significantly different from the results of the simulation method.Errors of up to 34% have been observed for amicroprocessor scoreboard circuit.This is due to the fact that the Q{crit} method assumesthat each node in the circuit is equally likely to be 0 or 1.The Q{crit} method can also missout logical masking within the circuit.Finally, a feasible method based on Monte-Carlo simulation is presented to estimate chip level SER in terms of Failure in Time (FIT) rate.