Communications of the ACM
Impossibility of distributed consensus with one faulty process
Journal of the ACM (JACM)
A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation
IEEE Transactions on Software Engineering
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Accurate Estimation of Soft Error Rate (SER) in VLSI Circuits
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Journal of Electronic Testing: Theory and Applications
Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era
IEEE Design & Test
Hardening Techniques against Transient Faults for Asynchronous Circuits
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Efficient Failure Detection in Pipelined Asynchronous Circuits
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Self-Stabilizing Microprocessor: Analyzing and Overcoming Soft Errors
IEEE Transactions on Computers
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic
IEEE Transactions on Computers
Analytical modeling of SRAM dynamic stability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Efficient analytical determination of the SEU-induced pulse shape
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits
IEEE Transactions on Dependable and Secure Computing
The use of triple-modular redundancy to improve computer reliability
IBM Journal of Research and Development
An analytical model for soft error critical charge of nanometric SRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining
EDCC '10 Proceedings of the 2010 European Dependable Computing Conference
Fault-tolerant algorithms for tick-generation in asynchronous logic: robust pulse generation
SSS'11 Proceedings of the 13th international conference on Stabilization, safety, and security of distributed systems
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
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We present the architecture and a detailed pre-fabrication analysis of a digital measurement ASIC facilitating long-term irradiation experiments of basic asynchronous circuits, which also demonstrates the suitability of the general approach for obtaining accurate radiation failure models developed in our FATAL project. Our ASIC design combines radiation targets like Muller C-elements and elastic pipelines as well as standard combinational gates and flip-flops with an elaborate on-chip measurement infrastructure. Major architectural challenges result from the fact that the latter must operate reliably under the same radiation conditions the target circuits are exposed to, without wasting precious die area for a rad-hard design. A measurement architecture based on multiple non-rad-hard counters is used, which we show to be resilient against double faults, as well as many triple and even higher-multiplicity faults. The design evaluation is done by means of comprehensive fault injection experiments, which are based on detailed Spice models of the target circuits in conjunction with a standard double-exponential current injection model for single-event transients (SET). To be as accurate as possible, the parameters of this current model have been aligned with results obtained from 3D device simulation models, which have in turn been validated and calibrated using micro-beam radiation experiments at the GSI in Darmstadt, Germany. For the latter, target circuits instrumented with high-speed sense amplifiers have been used for analog SET recording. Together with a probabilistic analysis of the sustainable particle flow rates, based on a detailed area analysis and experimental cross-section data, we can conclude that the proposed architecture will indeed sustain significant target hit rates, without exceeding the resilience bound of the measurement infrastructure.