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Microprocessors & Microsystems
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This paper presents a novel circuit fault detectionand isolation technique for quasi delay-insensitive asynchronouscircuits. We achieve fault isolation by a combinationof physical layout and circuit techniques. Theasynchronous nature of quasi delay-insensitive circuitscombined with layout techniques makes the design tolerantto delay faults. Circuit techniques are used to makesections of the design robust to non-delay faults. The combinationof these is an asynchronous defect-tolerant circuitwhere a large class of faults are tolerated, and the remainingfaults can be both detected easily and isolated to asmall region of the design.