Differential Fault Analysis of Secret Key Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Optical Fault Induction Attacks
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Fault Attacks on Dual-Rail Encoded Systems
ACSAC '05 Proceedings of the 21st Annual Computer Security Applications Conference
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers
IEEE Transactions on Computers
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique
Journal of Electronic Testing: Theory and Applications
Differential Behavioral Analysis
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Journal of Electronic Testing: Theory and Applications
Soft-error tolerance and mitigation in asynchronous burst-mode circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Recyclable PUFs: logically reconfigurable PUFs
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Asynchronous Logic Circuits and Sheaf Obstructions
Electronic Notes in Theoretical Computer Science (ENTCS)
Nanoscale technologies: prospect or hazard to dependable and secure computing?
LADC'07 Proceedings of the Third Latin-American conference on Dependable Computing
An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors & Microsystems
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This paper presents hardening techniques against fault attacks and the practical evaluation of their efficiency. The circuit technology investigated to improve the resistance against fault attacks is asynchronous logic. Specific properties of asynchronous circuits make them inherently resistant against a large class of faults. An analysis of their behavior in the presence of faults shows that they are an interesting alternative to design robust systems. A behavior diagnosis enables us to propose hardening techniques that improve fault tolerance and resistance. They are applied at design time and aim at exploiting quasi-delay insensitive (QDI) circuit properties to significantly harden the architecture with a very low area overhead and a reasonable performance penalty. To validate these techniques, a hardened DES crypto-processor is presented. The countermeasures are evaluated using laser beam fault injection.