A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique

Authors:
Rui Gong;Wei Chen;Fang Liu;Kui Dai;Zhiying Wang
Affiliations:
School of Computer, National University of Defense Technology, Changsha, PR China 410073;School of Computer, National University of Defense Technology, Changsha, PR China 410073;School of Computer, National University of Defense Technology, Changsha, PR China 410073;School of Computer, National University of Defense Technology, Changsha, PR China 410073;School of Computer, National University of Defense Technology, Changsha, PR China 410073
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2008

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Abstract

Some asynchronous circuit techniques are proposed to provide a new approach to Single Event Effect (SEE) tolerance in synchronous circuits. Two structures, Double Modular Redundancy (DMR) and Temporal Spatial Triple Modular Redundancy with Dual Clock Triggered Register (TSTMR-D), are presented. Three SEE tolerant 8051 cores with DMR, TSTMR-D and traditional Triple Modular Redundancy (TMR) are implemented in SMIC 0.35 μm process. The results of fault injection experiments indicate that DMR has a relatively low overhead on both area and latency than TMR, while tolerates SEU in sequential logic. TSTMR-D provides tolerance for both SEU and SET with reasonable area and latency overhead.