Self-timed is self-checking

Automatic generation of synchronous test patterns for asynchronous circuits

DAC '97 Proceedings of the 34th annual Design Automation Conference

Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique

Journal of Electronic Testing: Theory and Applications

Initialization-based test pattern generation for asynchronous circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Redundant logic insertion and latency reduction in self-timed adders

VLSI Design

Formal Asynchronous Systems Modelling

Fundamenta Informaticae