Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLAs
IEEE Transactions on Computers
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Using embedded FPGAs for SoC yield improvement
Proceedings of the 39th annual Design Automation Conference
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Asynchronous Design - An Interesting Alternative
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Cost-aware three-dimensional (3D) many-core multiprocessor design
Proceedings of the 47th Design Automation Conference
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This paper presents a systematic design for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the target asynchronous circuits on one planar device layer which is fabricated with aggressive technology, are built on fault tolerant graph models with extra spare resources, and can be reconfigured by autonomous reconfiguration logic on another planar device layer which is fabricated with conservative technology, in the presence of hard errors. The yield analysis shows that this method can result in 20--30% overall yield enhancement. This design methodology can be conveniently applied to clocked designs without significant changes.