Translating programs into delay-insensitive circuits
Translating programs into delay-insensitive circuits
Introduction to VLSI Systems
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
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The fundamental assumptions of synchronous design have been under some scrutiny of late. Every synchronous designer must assume: all signals are binary and time is discrete. Many designers are realizing that most of their problems surround these basic assumptions. Problems which seriously impact their final results include clock skew, power consumption, and critical path delays. Asynchronous design offers an interesting alternative by keeping the assumption that signals are binary but removing the assumption that time is discrete. Asynchronous design as an alternative to synchronous design is a theoretical realization that warrants some attention. In the past asynchronous design was thought to be impractical, but now that several methodologies have been published and CAD algorithms developed, many believe there is new hope for asynchronous designs. Most believe that coupling asynchronous design with synchronous design is the most practical. The author highlights some of the methodologies and CAD algorithms published to date.