The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis

Authors:
R. Leveugle;Z. Koren;I. Koren;G. Saucier;N. Wehn
Affiliations:
Institut National Polytechnique de Grenoble/CSI, Grenoble, France;Univ. of Massachusetts, Amherst;Univ. of Massachusetts, Amherst;Institut National Polytechnique de Grenoble/CSI, Grenoble, France;Darmstadt Univ. of Technology, Darmstadt, Germany/ and Siemens AG, Munich, Germany
Venue:
IEEE Transactions on Computers
Year:
1994

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Abstract

This paper summarizes a practical experiment in designing a defect tolerant microprocessor and presents the underlying principles. Unlike memory integrated circuits, microprocessors have an irregular structure which complicates both the task of incorporating redundancy for defect tolerance in the design and the task of analyzing the resulting yield increase. The main goal of this paper is to present the detailed yield analysis of a defect tolerant microprocessor with an irregular structure which has been successfully fabricated. The approaches employed for achieving the goal of yield enhancement in the data path and the control part of the microprocessor are described first. Then, the yield enhancement due to the incorporated redundancy is analyzed. Finally, some practical and theoretical conclusions are drawn.