A defect-tolerant and fully testable PLA
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Spare allocation and reconfiguration in large area VLSI
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis
IEEE Transactions on Computers
An Improved Analytical Yield Evaluation Method for Redundant RAM's
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Opportunities and challenges in application-tuned circuits and architectures based on nanodevices
Proceedings of the 1st conference on Computing frontiers
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
| Hi-index | 14.98 |
Reconfigurable logic and memory structures are an important means of increasing manufacturing yield as both circuit density and chip size continue to increase. Yield enhancement through reconfiguration, however, necessarily relies on accurate diagnosis of fault locations. Although a substantial body of literature exists concerning testing of logic arrays, little is known regarding diagnosis of the specific locations of multiple faults in such arrays. In the paper a fault diagnosis algorithm is presented for large programmable logic arrays (PLAs).