Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Design for yield enhancement and reconfiguration in large area VLSI/WSI architectures (Diagnosis).
Design for yield enhancement and reconfiguration in large area VLSI/WSI architectures (Diagnosis).
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Diagnosis and Repair of Memory with Coupling Faults
IEEE Transactions on Computers
Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLAs
IEEE Transactions on Computers
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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One approach to enhancing the yield of large area VLSI is through design for yield enhancement by means of restructurable interconnect, logic and computational elements. Although extensive literature exists concerning architectural design for inclusion of spares and restructuring mechanisms in memories and processor arrays, little research has been published on optimal spare allocation and reconfiguration in the presence of multiple defects. In this paper, a summary of a systematic approach developed by the authors for spare allocation and reconfiguration is presented. Spare allocation is modeled in graph theoretic terms in which spare allocation for a specific reconfigurable system is shown to be equivalent to either a graph matching or a graph dominating set problem. The complexity of optimal spare allocation for each of the problem classes is analyzed in this paper and reconfiguration algorithms are provided.