Fault Tolerance in VLSI Circuits
Computer
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis
IEEE Transactions on Computers
A defect-tolerant and fully testable PLA
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure
IEEE Design & Test
An Efficient Method for Improving Reliability of a Pipeline FFT
IEEE Transactions on Computers
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement
ATS '09 Proceedings of the 2009 Asian Test Symposium
A new paradigm for trading off yield, area and performance to enhance performance per wafer
Proceedings of the Conference on Design, Automation and Test in Europe
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Increasing yield is important, especially for nano-scale technologies. Also, pipelines are an important aspect of many SoC architectures. In this paper we present new approaches to improve the yield and yield/area of pipeline architectures by using (1) an appropriate number of redundant copies for each module, and (2) sufficient steering logic resources. We present an optimal algorithm of time complexity O(n3) that adds redundant modules to an n-stage pipeline so as to maximize yield. Experimental results indicate that for parameter values of interests, this algorithm also improves the yield/area of the pipeline, especially when the yield for some modules is low.