Configurable isolation: building high availability systems with commodity multi-core processors
Proceedings of the 34th annual international symposium on Computer architecture
An Illustrated Methodology for Analysis of Error Tolerance
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe
Amdahl's Law in the Multicore Era
Computer
The use of triple-modular redundancy to improve computer reliability
IBM Journal of Research and Development
SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement
ATS '09 Proceedings of the 2009 Asian Test Symposium
Hardware that produces bounded rather than exact results
Proceedings of the 47th Design Automation Conference
Approximate logic synthesis for error tolerant applications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Salvaging chips with caches beyond repair
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we outline a novel way to 1) predict the revenue associated with a wafer, 2) maximize the projected revenue through unconventional yield enhancement techniques, and 3) produce dice from the same mask that may have different performances and selling prices. Unlike speed binning, such heterogeneity is intentional by design. To achieve these goals we overturn the traditional concepts of redundancy, and present a novel design flow for yield enhancement called "Reduced Redundancy Insertion", where spares can potentially have less area and performance than their fathers. We develop a model for the revenue associated with the new design methodology that integrates system configuration and leverages yield, area and performance. The primary metric used in this model is termed "Expected Performance per Area", which is a measure that can be reliably estimated for different system architectures, and can be maximized by using algorithms proposed in this paper. We present theoretical models and case studies that characterize our designs, and experimental results that validate our prediction. We show that using Reduced Redundancy can improve wafer revenue by 10--30%.