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Quantum computation and quantum information
Quantum computation and quantum information
Modeling, Analysis, and Self-Management of Electronic Textiles
IEEE Transactions on Computers
Analysis and Testing for Error Tolerant Motion Estimation
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Threshold testing: Covering bridging and other realistic faults
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology
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Energy-efficient motion estimation using error-tolerance
Proceedings of the 2006 international symposium on Low power electronics and design
Estimating Error Rate in Defective Logic Using Signature Analysis
IEEE Transactions on Computers
Reduction of detected acceptable faults for yield improvement via error-tolerance
Proceedings of the conference on Design, automation and test in Europe
An Illustrated Methodology for Analysis of Error Tolerance
IEEE Design & Test
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Proceedings of the conference on Design, automation and test in Europe
A platform-based design environment for synthetic biological systems
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Irregular designs for two-state systematic with serial concatenated parity codes
MILCOM'06 Proceedings of the 2006 IEEE conference on Military communications
Dynamic effort scaling: managing the quality-efficiency tradeoff
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MACACO: modeling and analysis of circuits for approximate computing
Proceedings of the International Conference on Computer-Aided Design
Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
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Proceedings of the Conference on Design, Automation and Test in Europe
On reconfiguration-oriented approximate adder design and its application
Proceedings of the International Conference on Computer-Aided Design
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Technological achievements have made it possible to: fabricate CMOS circuits with over a billion transistors; implement Boolean operations using quantum devices and/or the spin of an electron; implement transformations using bio and molecular based cells. Problems with many of these technologies are due to such factors as process variations, defects and impurities in materials and solutions, and noise. Consequently, many systems built from these technologies operate imperfectly. Luckily there are many complex and large-market systems (applications) that tolerate acceptable though not always correct results. In addition, there is emerging a body of mathematical analysis related to imperfect computation. In this paper we first introduce the concepts of acceptable error-tolerance and acceptable performance degradation, and demonstrate how important attributes of these concepts can be quantified. We interlace this discussion with several examples of systems that can effectively employ these two concepts. Next we mention several immerging technologies that motivate the need to study these concepts as well as related mathematical paradigms. Finally we will list a few CAD issues that are needed to support this new form of technological revolution.