Threshold testing: improving yield for nanoscale VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware that produces bounded rather than exact results
Proceedings of the 47th Design Automation Conference
Error Rate Estimation for Defective Circuits via Ones Counting
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A new paradigm for trading off yield, area and performance to enhance performance per wafer
Proceedings of the Conference on Design, Automation and Test in Europe
AppAdapt: opportunistic application adaptation in presence of hardware variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Error tolerance deals with the use of defective circuitry that occasionally produces errors, yet provides acceptable performance to users when executing certain applications. Although this concept may seem unappealing, it has been used for some time in several digital systems associated with multimedia signals, such as sound and images. The motivation for using such devices is the related increase in effective yield, and hence lower-cost parts. This article presents a methodology for the analysis of the applicability of error tolerance. The methodology is illustrated with respect to a digital telephone-answering device, but is applicable to a broad class of systems. Key components of this methodology include defining acceptable yet imperfect behavior, determining if a large class of realistic defects in a subsystem provide acceptable behavior at the system level, and determining how to recognize (test) whether a defective subsystem will provide acceptable system performance.