Exploiting Omissive Faults in Synchronous Approximate Agreement
IEEE Transactions on Computers
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Determining error rate in error tolerant VLSI chips
DELTA '04 Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications
Defect and Error Tolerance in the Presence of Massive Numbers of Defects
IEEE Design & Test
Intelligible Test Techniques to Support Error-Tolerance
ATS '04 Proceedings of the 13th Asian Test Symposium
Energy Aware Computing through Probabilistic Switching: A Study of Limits
IEEE Transactions on Computers
Analysis and Testing for Error Tolerant Motion Estimation
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Threshold testing: Covering bridging and other realistic faults
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Journal of VLSI Signal Processing Systems
Estimating Error Rate in Defective Logic Using Signature Analysis
IEEE Transactions on Computers
An Illustrated Methodology for Analysis of Error Tolerance
IEEE Design & Test
Ones Counting Based Error-Rate Estimation for Multiple Output Circuits
NDCS '08 Proceedings of the 2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems
Online circuit reliability monitoring
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Architecture Design for Soft Errors
Architecture Design for Soft Errors
A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic
DELTA '10 Proceedings of the 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications
Arithmetic built-in self-test for DSP cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With VLSI circuit feature size scaling down, it is becoming more difficult and expensive to achieve a desired level of yield. Error-tolerance employs defective chips that occasionally produce erroneous yet acceptable results in targeted applications, and has been proposed as one way to increase effective yield. These chips are characterized by criteria set by specific applications. Error rate, an upper-bound on how frequent errors occur at an output, is one such criterion. In this article we focus on the following problem: given a combinational logic circuit that is defective, and hence occasionally produces an erroneous output, how can we determine the error rate of each output line by using ones counting? The results of this work can also be used for runtime error estimation in aging systems and in environments where soft-errors are produced.