Modeling, Analysis, and Self-Management of Electronic Textiles
IEEE Transactions on Computers
Determining error rate in error tolerant VLSI chips
DELTA '04 Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications
Defect and Error Tolerance in the Presence of Massive Numbers of Defects
IEEE Design & Test
Intelligible Test Techniques to Support Error-Tolerance
ATS '04 Proceedings of the 13th Asian Test Symposium
Analysis and Testing for Error Tolerant Motion Estimation
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Mathematical Theory of Communication
A Mathematical Theory of Communication
Hardware that produces bounded rather than exact results
Proceedings of the 47th Design Automation Conference
Error Rate Estimation for Defective Circuits via Ones Counting
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.98 |
As feature size approaches molecular dimensions and the number of devices per chip reaches astronomical values, VLSI manufacturing yield significantly decreases. This motivates interests in new computing models. One such model is called error tolerance. Classically, during the postmanufacturing test process, chips are classified as being bad (defective) or good. The main premise in error-tolerant computing is that some bad chips that fail classical go/no-go tests and do indeed occasionally produce erroneous results actually provide acceptable performance in some applications. Thus, new test techniques are needed to classify bad chips according to categories based upon their degree of acceptability with respect to predetermined applications. One classification criterion is error rate. In this paper, we first describe a simple test structure that is a minor extension to current scan-test and built-in self-test structures and that can be used to estimate the error rate of a circuit. We then address three theoretical issues. First, we develop an elegant mathematical model that describes the key parameters associated with this test process and incorporates bounds on the error in estimating error rate and the level of confidence in this estimate. Next, we present an efficient testing procedure for estimating the error rate of a circuit under test. Finally, we address the problem of assigning bad chips to bins based on their error rate. We show that this can be done in an efficient, hence cost-effective, way and discuss the quality of our results in terms of such concepts as increase effective yield, yield loss, and test escape.